APU2 user manual mentions that nct5104d has a watchdog function and that pins 5 & 6 of J2 header need to be shorted to enable it.
According to the schematic that should connect WDTO pin of the superio to the reset signal.
So, I guess that a low signal on WDTO should reset the system.
The problem is that there is never a low signal on pin 6.
I am using FreeBSD wbwd dirver. And I can inspect the relevant configuration registers in LDN 8. If the watchdog daemon is killed, I can see how the watchdog timer runs down to zero (register F1h) and then I see that the watchdog timeout status gets set (bit 4 in F2h). However, there is no low pulse on pin 6 of J2 when that happens. I checked that by using a logic analyzer. I don't know what the problem is. Either that pin is incorrectly wired or nct5104d does not pulse its WDTO pin (pin 22).
Another observation is that if I configure one of multi-function pins to carry WDTO signal, then I can see a low pulse of approximately 100 ms at that pin.
For example, I configured GP01 (which is routed to pin 4 of J17 GPIO header) in that fashion. I set bit 1 of configuration register E0h in LDN 8.
Of course, after that the pin no longer works as a general purpose I/O.
Could you please clarify what is going on with respect to the watchdog functionality and WDTO signal of nct5104d on APU2 ?
Another surprise for me was that I couldn't use GP11 (pin 12 of the GPIO header) as a general pupose I/O by default.
It turns out that it is configured for a BEEP function. I guess that the firmware does that.
I needed to clear bit 1 of E1h register in LDN 8 to get full control over it.