APU2 uses AMD GX-412TC SoC that belong to family 16h model 30h.
According to the BKDG for that model, the HPET timers on that SoC should be capable of FSB interrupt delivery:
15 TmrFsbCap. Read-only. Reset: 1. 1=Front side bus delivery is supported.
The value is hard-wired, even.
However, on my APU2 I see that that bit cleared.
I am intrigueud, how did you managed to do that?
And more importantly, why?
I think that the FSB mode is much more convenient than the regular interrupt mode that requires interrups to go through IO-APIC.